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Convolution Encoder Implementation using FPGA

S. S. Podutwar, H. M. Baradkar, V. R. Thakare Published in Communication

IJAIS Proceedings on National Level Technical Conference X-PLORE 2013
Year of Publication: 2013
© 2012 by IJAIS Journal
Series XPLORE
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  1. S S Podutwar, H M Baradkar and V R Thakare. Article: Convolution Encoder Implementation using FPGA. IJAIS Proceedings on National Level Technical Conference X-PLORE 2013 XPLORE:17-24, March 2013. BibTeX

    @article{key:article,
    	author = "S. S. Podutwar and H. M. Baradkar and V. R. Thakare",
    	title = "Article: Convolution Encoder Implementation using FPGA",
    	journal = "IJAIS Proceedings on National Level Technical Conference X-PLORE 2013",
    	year = 2013,
    	volume = "XPLORE",
    	pages = "17-24",
    	month = "March",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

Convolution encoding is a Forward Error Correction (FEC) technique used in continuous one-way and real time communication links. It can provide substantial improvement in bit error rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices. This thesis documents the development of a programmable convolution encoder implemented in a Field Programmable Gate Array (FPGA) from Xilinx, Inc. , called the XC2S100. The encoder is capable of coding a digital data stream with any one of 39 convolution codes. The encoder is made up of the combinational and sequential logic circuits. The design is simplified so that FPGA implementation of this encoder is simpler. We have written the VHDL code for convolution encoder and results are tested on FPGA kit for simulation and synthesis.

Reference

  1. VHDL Primer , J. Bhaskar
  2. Logic and computer Design by M. Morris Mano, C. R. Kime
  3. Circuit Design with VHDL by Douglas Perry.
  4. VHDL by Brown & Vranesic
  5. Digital Communication by Simon Haykin

Keywords

FPGA, VHDL,Encoder