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Reseach Article

Design and Simulation of Scalable Fast Parallel Counter

by Gifty John B, Kashwan K. R
International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 1 - Number 9
Year of Publication: 2012
Authors: Gifty John B, Kashwan K. R
10.5120/ijais12-450219

Gifty John B, Kashwan K. R . Design and Simulation of Scalable Fast Parallel Counter. International Journal of Applied Information Systems. 1, 9 ( April 2012), 28-33. DOI=10.5120/ijais12-450219

@article{ 10.5120/ijais12-450219,
author = { Gifty John B, Kashwan K. R },
title = { Design and Simulation of Scalable Fast Parallel Counter },
journal = { International Journal of Applied Information Systems },
issue_date = { April 2012 },
volume = { 1 },
number = { 9 },
month = { April },
year = { 2012 },
issn = { 2249-0868 },
pages = { 28-33 },
numpages = {9},
url = { https://www.ijais.org/archives/volume1/number9/118-0219/ },
doi = { 10.5120/ijais12-450219 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T10:42:02.384997+05:30
%A Gifty John B
%A Kashwan K. R
%T Design and Simulation of Scalable Fast Parallel Counter
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 1
%N 9
%P 28-33
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this research paper, we report an entirely different approach to design a scalable fast parallel counter with improved performance in terms of component and transistor counts. Subsequently the simulation tests are carried out for a wide range of input conditions to validate the design. The main advantages of this scalable counter include low power consumption in milliwatt (mw) range and have speed in the range of GHz. The proposed design is modular in nature indicating that it can easily be upgraded or applied for large counters easily. Repeated use of basic building blocks such as 3-bit synchronous parallel counter, simple D flip flop and 2-bit synchronous parallel counter with enable signal made the design of counter simpler and modular. The logic uses early overflow states enabling all the blocks in the architecture concurrently at the system clock. The pipelined structures together with early overflow based logic provide correct functioning of all building blocks without ripple effects. The design is implemented using Microwind, Digital Schematics (DSCH) and 0. 12 µm technologies. Performance shows a total power consumption of 0. 164 mw with a clock speed of 1GHz.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Early Overflow State Counter Width Counting Path State Look-ahead Logic Digital Circuits Chip Area.