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Design and Simulation of Scalable Fast Parallel Counter

Gifty John B, Kashwan K. R Published in

International Journal of Applied Information Systems
Year of Publication 2012
© 2010 by IJAIS Journal
Info Co-published with IJCA
10.5120/ijais12-450219
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  1. Gifty John B and Kashwan K R. Article: Design and Simulation of Scalable Fast Parallel Counter. International Journal of Applied Information Systems 1(9):28-33, April 2012. BibTeX

    @article{key:article,
    	author = "Gifty John B and Kashwan K. R",
    	title = "Article: Design and Simulation of Scalable Fast Parallel Counter",
    	journal = "International Journal of Applied Information Systems",
    	year = 2012,
    	volume = 1,
    	number = 9,
    	pages = "28-33",
    	month = "April",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

In this research paper, we report an entirely different approach to design a scalable fast parallel counter with improved performance in terms of component and transistor counts. Subsequently the simulation tests are carried out for a wide range of input conditions to validate the design. The main advantages of this scalable counter include low power consumption in milliwatt (mw) range and have speed in the range of GHz. The proposed design is modular in nature indicating that it can easily be upgraded or applied for large counters easily. Repeated use of basic building blocks such as 3-bit synchronous parallel counter, simple D flip flop and 2-bit synchronous parallel counter with enable signal made the design of counter simpler and modular. The logic uses early overflow states enabling all the blocks in the architecture concurrently at the system clock. The pipelined structures together with early overflow based logic provide correct functioning of all building blocks without ripple effects. The design is implemented using Microwind, Digital Schematics (DSCH) and 0. 12 µm technologies. Performance shows a total power consumption of 0. 164 mw with a clock speed of 1GHz.

Reference

  1. S. Abdel-Hafeez and Ann Gordon-Ross, "A digital CMOS parallel counter architecture based on state look-ahead logic,"in Proc. IEEE VLSI Systems, vol. 19, no. 6, pp. 1023-133.
  2. S. Abdel-Hafeez, S. Harb and W. Eisenstadt, "High speed digital CMOS divide-by-N frequency divider," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2008, pp. 592-595.
  3. D. Zhang, G. Jullien, W. Miller and E. Swartzlander,"Arithmetic for digital neural networks," in Proc. IEEE 10th Symp. Comput. Arith, June1991, pp. 58-63.
  4. N. Nikityuk, "Use of parallel counters for triggering nuclear instruments and methods in physics research," vol. A321, no. 3, pp. 571-582, Oct 1992.
  5. M. D. Ercegovac and T. Lang , Digital Arithmetic. San Mateo, CA: Mogan Kaufmann, 2004.
  6. M. R. Stan," Synchronous up/down counter with period independent of counter size," in Proc. IEEE Symp. Comput. Arith, Asilomar, CA, Jul. 1997, pp. 274-281.
  7. B. Parhami, computer Arithmetic: Algorithms and Hardware Designd. London, U. K: Oxford Univ. Press, 2000.
  8. A. P. Kakarountas, G. Theodoridis, K. S. Papadomanolakis and C. E. Goutis, "A novel high –speed counter with counting rate independent of the counter's length," in Proc. IEEE International Confrence on Electronics Circuit and Systems, (ICECS), UAE, Dec. 2003, pp. 1164-1167.
  9. www. microwind. net. Web page of the main software used.
  10. B. Razavi, RF Microelectronics. Upper Saddlle River, NJ: Prentice-Hall, 1998.
  11. M. Alioto. R. Mita and W. Eisenstadt, "Design of high speed power efficient MOS current-mode logic frequency dividers" IEEE Transactions on Circuits and Systems, II, Expr. Briefs, vol 53, No 11, pages 1165 – 1169 Nov 2006

Keywords

Early Overflow State, Counter Width, Counting Path, State Look-ahead Logic, Digital Circuits, Chip Area.