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Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7

Husainali S. Bhimani, Hitesh N. Patel, Abhishek A. Davda. Published in Circuits and Systems

International Journal of Applied Information Systems
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Husainali S. Bhimani, Hitesh N. Patel, Abhishek A. Davda
10.5120/ijais2016451550
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  1. Husainali S Bhimani, Hitesh N Patel and Abhishek A Davda. Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7. International Journal of Applied Information Systems 10(9):26-37, May 2016. URL, DOI BibTeX

    @article{10.5120/ijais2016451550,
    	author = "Husainali S. Bhimani and Hitesh N. Patel and Abhishek A. Davda",
    	title = "Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7",
    	journal = "International Journal of Applied Information Systems",
    	issue_date = "May 2016",
    	volume = 10,
    	number = 9,
    	month = "May",
    	year = 2016,
    	issn = "2249-0868",
    	pages = "26-37",
    	numpages = 12,
    	url = "http://www.ijais.org/archives/volume10/number9/892-2016451550",
    	doi = "10.5120/ijais2016451550",
    	publisher = "Foundation of Computer Science (FCS), NY, USA",
    	address = "New York, USA"
    }
    

Abstract

Reduced Instruction Set Compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. This paper presents 32 bit 3 stage architecture inspired by MIPS. The Idea of this paper is to implement custom architecture like MIPS 32 bit architecture in VERILOG HDL. The last step is to implement MIPS on FPGA (Field programmable gate array). MIPS (Microprocessor without Interlocked pipeline stages) processors are one of the first successful classical RISC architecture.

Reference

  1. David A. Patterson, John L. Hennessy 2005. Computer organization and design, 3rd Edition, Elsevier.
  2. Sharda P. Katke, G.P. Jain,"Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor", IJETAE, Volume 2. Issue 4. April 2012, pp. 340-346.
  3. Preetam Bhosle, Hari Krishna Moorthy, "FPGA Implementation of low power pipelined 32-bit RISC Processor", International Journal of Innovative Technology and Exploring Engineering (IJITEE), August 2012.
  4. Bai-ZhongYing, Computer Organization, Science Press, 2000.11.
  5. Charles E. Gimarc, Veljko M. Mhtinovic, "RISC Principles, Architecture, and Design", Computer Science Press Inc., 1989.

Keywords

MIPS, RISC, FPGA, VERILOG HDL.