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Sobel Edge Detection using Parallel Architecture based on FPGA

Varun Sanduja, Rajeev Patial Published in Image Processing

International Journal of Applied Information Systems
Year of Publication 2012
© 2010 by IJAIS Journal
10.5120/ijais12-450515
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  1. Varun Sanduja and Rajeev Patial. Article: Sobel Edge Detection using Parallel Architecture based on FPGA. International Journal of Applied Information Systems 3(4):20-24, July 2012. BibTeX

    @article{key:article,
    	author = "Varun Sanduja and Rajeev Patial",
    	title = "Article: Sobel Edge Detection using Parallel Architecture based on FPGA",
    	journal = "International Journal of Applied Information Systems",
    	year = 2012,
    	volume = 3,
    	number = 4,
    	pages = "20-24",
    	month = "July",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

This paper proposes an FPGA based approach known as Sobel Edge Detection. RGB image is taken by the computer source and converted into binary image using MATLAB. The proposed Sobel Edge Detection is modeled using Parallel Architecture and implemented in Verilog HDL. The whole process is performed in the hardware level that utilizes the resources of Xilinx ISE 12. 4. The result shows good performance of edge detection with maximum frequency of 200 MHz. The time from image read to final edge determined image would vary with the image size. Also, the device utilization summary shows good results.

Reference

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Keywords

Gradient Operator, Sobel Edge Detection, Digital Image Processing, FPGA