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Multi-Bit Upset Deduction/Correction for Memory Applications

X. Jushwanth Xavier, Lakshmi Kantham Published in Circuits And Systems

International Journal of Applied Information Systems
Year of Publication: 2013
© 2012 by IJAIS Journal
10.5120/ijais12-450865
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  1. Jushwanth X Xavier and Lakshmi Kantham. Article: Multi-Bit Upset Deduction/Correction for Memory Applications. International Journal of Applied Information Systems 5(3):15-18, February 2013. BibTeX

    @article{key:article,
    	author = "X. Jushwanth Xavier and Lakshmi Kantham",
    	title = "Article: Multi-Bit Upset Deduction/Correction for Memory Applications",
    	journal = "International Journal of Applied Information Systems",
    	year = 2013,
    	volume = 5,
    	number = 3,
    	pages = "15-18",
    	month = "February",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

In electronics memories are the widely used elements. As the transistor size shrinks multiple-bit upset (MCUs) are increasing due to radiation effects in memories. This affects the reliability of memories. Interleaving and built-in current sensors (BICS) have been success in the case of single event upset (SEC). The process is taken one step further by proposing specific error correction codes to protect memories against multiple-bit upsets and to improve yield have been proposed. The method is evaluated using fault injection experiments. The results are compared with known techniques such as Hamming codes. The proposed codes provide a better performance compared to that of the hamming codes in terms of Single Event Upset. In the case of the Multi Bit Upset it provides better coverage in error deduction and correction schemes.

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Keywords

Multi-bit error correction, Single event upset, hamming codes