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Reseach Article

Multi-Bit Upset Deduction/Correction for Memory Applications

by X. Jushwanth Xavier, Lakshmi Kantham
International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 5 - Number 3
Year of Publication: 2013
Authors: X. Jushwanth Xavier, Lakshmi Kantham
10.5120/ijais12-450865

X. Jushwanth Xavier, Lakshmi Kantham . Multi-Bit Upset Deduction/Correction for Memory Applications. International Journal of Applied Information Systems. 5, 3 ( February 2013), 15-18. DOI=10.5120/ijais12-450865

@article{ 10.5120/ijais12-450865,
author = { X. Jushwanth Xavier, Lakshmi Kantham },
title = { Multi-Bit Upset Deduction/Correction for Memory Applications },
journal = { International Journal of Applied Information Systems },
issue_date = { February 2013 },
volume = { 5 },
number = { 3 },
month = { February },
year = { 2013 },
issn = { 2249-0868 },
pages = { 15-18 },
numpages = {9},
url = { https://www.ijais.org/archives/volume5/number3/425-0865/ },
doi = { 10.5120/ijais12-450865 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T16:01:17.717390+05:30
%A X. Jushwanth Xavier
%A Lakshmi Kantham
%T Multi-Bit Upset Deduction/Correction for Memory Applications
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 5
%N 3
%P 15-18
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In electronics memories are the widely used elements. As the transistor size shrinks multiple-bit upset (MCUs) are increasing due to radiation effects in memories. This affects the reliability of memories. Interleaving and built-in current sensors (BICS) have been success in the case of single event upset (SEC). The process is taken one step further by proposing specific error correction codes to protect memories against multiple-bit upsets and to improve yield have been proposed. The method is evaluated using fault injection experiments. The results are compared with known techniques such as Hamming codes. The proposed codes provide a better performance compared to that of the hamming codes in terms of Single Event Upset. In the case of the Multi Bit Upset it provides better coverage in error deduction and correction schemes.

References
  1. Hareland, S. , Maiz, J. , Alavi, Mistry, K. , Walsta, S. , Changhong Dai, "Impact of CMOS process scaling and SOI on the soft error rates of logic processes", VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on, 73 - 74
  2. Cardarilli, G. , Leandri, A, Marinucci, P. , M. Ottavi, Pontarelli, S. , M. Re, and Salsano, A. , "Design of a fault tolerant solid state mass memory," IEEE Transactions on Reliability. , vol. 52, no. 4, pp. 476–491, Dec. 2003.
  3. Ferreyra, P. A. , Marques, C. A. , Ferreyra, R. T. , Gaspar, J. P. , "Failure map functions and accelerated mean time to failure tests: New approaches for improving the reliability estimation in systems exposed to single event upsets," IEEE Trans. Nucl. Sci. , vol. 52, no. 1, pp. 494–500, Jan. 2005.
  4. Hazucha, P. , Svensson, C. "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. Nucl. Sci. , vol. 47, no. 6, pp. 2586–2594, Dec. 2000.
  5. Karlsson, J. , Liden, P. , Dahlgren, P. , Johansson, R. , Gunneflo, U. "Using heavy-ion radiation to validate fault-handling mechanisms," IEEE Trans. Microelectron. , vol. 14, pp. 8–23, 1994.
  6. Reed, R. A. , Carts, M. A. , Marshall, P. W. , Marshall, C. J. , Musseau, O. , McNulty, P. J. , Roth, D. R. , Buchner, S. , Melinger, J. , Corbiere, T. "Heavy ion and proton-induced single event multiple upset," IEEE Trans. Nucl. Sci. , vol. 44, no. 6, pp. 2224–2229, Dec. 1997.
  7. Seifert, N. , Moyer, D. , Leland, N. , Hokinson, R. "Historical trend in alpha-particle induced soft error rates of the Alpha microprocessor," in Proc. 39th Annu. IEEE Int. Reliab. Phys. Symp. , 2001, pp. 259–265.
  8. Satoh, S. , Tosaka, Y. , Wender, S. A. "Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's" IEEE Electron Device Lett. , vol. 21, no. 6, pp. 310–312, 2000.
  9. Dutta, A. , Touba, N. A. "Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code. " in Proc. IEEE VLSI Test Symp. (VTS), 2007, pp. 349–354.
  10. Nicolaidis, M. , Vargas, F. , Courtois, B. "Design of built-in current sensors for concurrent checking in radiation environments," IEEE Trans. Nucl. Sci. , vol. 40, no. 6, pp. 1584–1590, Dec. 1993.
  11. Lo, J,. "Analysis of a BICS-only concurrent error detection method," IEEE Trans. Computers, vol. 51, no. 3, pp. 241–253, 2002.
  12. Lu, S. K. , "Efficient built-in redundancy analysis for embedded memories with 2-D redundancy," IEEE Trans. Very Large Scale Integr. (VLSI) Systems, vol. 14, no. 1, pp. 34–42, Jan. 2006.
  13. Shyue-Kung Lu, Shih-Chang Huang, "Built-in self-test and repair (BISTR) techniques for embedded RAMs," in Proc. Int. Workshop, Memory Technol. Des. Test. , Aug. 2004, pp. 60–64.
  14. Argyrides, C. , Al-Yamani, A. , Lisboa, C. , Carro, L. , Pradhan, D. "Increasing memory yield in future technologies through innovative design," in Proc. 8th Int. Symp. Quality Electron. Des. (ISQED), Mar. 2009, pp. 622–626.
  15. Elmer, B. , Tchon, W. , Denboer, A. , Kohyama, S. , Hirabayashi, K. , Nojima, I. "Fault tolerant 92160 bit multiphase ccd memory," in IEEE Int. Conf. Solid-State Circuits. Dig. Techn. Papers, Feb. 1977, 116–117.
Index Terms

Computer Science
Information Sciences

Keywords

Multi-bit error correction Single event upset hamming codes