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FPGA based Hardware Implementation of Variant DPCM Image Compression Technique (Multiple LUT-DPCM)

Vandana Chahar, Seema Narwal Published in Signal Processing

International Journal of Applied Information Systems
Year of Publication: 2014
© 2013 by IJAIS Journal
10.5120/ijais14-451126
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  1. Vandana Chahar and Seema Narwal. Article: FPGA based Hardware Implementation of Variant DPCM Image Compression Technique (Multiple LUT-DPCM). International Journal of Applied Information Systems 7(1):16-19, April 2014. BibTeX

    @article{key:article,
    	author = "Vandana Chahar and Seema Narwal",
    	title = "Article: FPGA based Hardware Implementation of Variant DPCM Image Compression Technique (Multiple LUT-DPCM)",
    	journal = "International Journal of Applied Information Systems",
    	year = 2014,
    	volume = 7,
    	number = 1,
    	pages = "16-19",
    	month = "April",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

This paper proposed FPGA implementation of variant DPCM based image compression technique (Multiple LUT-DPCM). Image compression addresses the problem of reducing the amount of data required to represent a digital image. Such data compression can be achieved by reducing the redundancies of the image data in order to be able to store or transmit data in an efficient form. There are various onboard data compression techniques used in image processing. Out of which DPCM based compression technique is the most commonly used one. For the hardware implementation, an algorithm for Multiple LUT DPCM is designed. VHDL code is developed based on the algorithm designed. After simulation and verification of developed code with test data generated, it implemented in to hardware. The developed hardware's functionality, then verified with the already simulated data and also with real image data.

Reference

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Keywords

Image Compression, Redundancies, LUT, Differential Pulse Code Modulation (DPCM), FPGA