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Design of SD/eMMC Protocol Compliance Solutions

Aparna N, Mamatha H R, Dheerendra Singh Tomar, Rakesh Kumar Published in Circuits And Systems

International Journal of Applied Information Systems
Year of Publication: 2014
© 2013 by IJAIS Journal
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  1. Aparna N, Mamatha H R, Dheerendra Singh Tomar and Rakesh Kumar. Article: Design of SD/eMMC Protocol Compliance Solutions. International Journal of Applied Information Systems 7(7):33-36, August 2014. BibTeX

    	author = "Aparna N and Mamatha H R and Dheerendra Singh Tomar and Rakesh Kumar",
    	title = "Article: Design of SD/eMMC Protocol Compliance Solutions",
    	journal = "International Journal of Applied Information Systems",
    	year = 2014,
    	volume = 7,
    	number = 7,
    	pages = "33-36",
    	month = "August",
    	note = "Published by Foundation of Computer Science, New York, USA"


Protocol Validation is an important step in validating the I/O interface of the System on Chip (SoC). In developing the protocol compliance solutions for validating the Secure Digital/Embedded Multi Media Controller (SD/eMMC) protocol, the main intention is to capture the behavior of protocol under various physical conditions using a Logic Analyzer (LA). LA facilitates more capture of data and offers more number of channels and is more cost effective compared to existing Digital Storage Oscilloscope (DSO) methodology. In addition to decode, the solution is capable of carrying out the analysis of the data captured and decoded from LA. Analysis functionality includes command-response analysis, cyclic redundancy check, integrity check and flow analysis that assess and reports the functionality and performance of the protocol under variations of temperature & voltage conditions. Analyzer helps in tracing out all kind of deviations from the specifications and standards defined for SD and eMMC.


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Digital Storage Oscilloscope Embedded Multi Media Controller, Logic Analyzer, Secure Digital, System on Chip.