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Basic Digital Logic Gate Design using Carbon Nanotube Field Effect Transistors

Y. Srinivasa Rao, Ram Babu. Busi Published in Advanced Computing

IJAIS Proceedings on International Conference and workshop on Advanced Computing 2014
Year of Publication: 2014
© 2014 by IJAIS Journal
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  1. Srinivasa Y Rao and Ram Babu. Busi. Article: Basic Digital Logic Gate Design using Carbon Nanotube Field Effect Transistors. IJAIS Proceedings on International Conference and workshop on Advanced Computing 2014 ICWAC 2014(1):1-5, June 2014. BibTeX

    @article{key:article,
    	author = "Y. Srinivasa Rao and Ram Babu. Busi",
    	title = "Article: Basic Digital Logic Gate Design using Carbon Nanotube Field Effect Transistors",
    	journal = "IJAIS Proceedings on International Conference and workshop on Advanced Computing 2014",
    	year = 2014,
    	volume = "ICWAC 2014",
    	number = 1,
    	pages = "1-5",
    	month = "June",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

In this paper, the performance of ambipolar carbon nanotube field effect transistor based logic devices have been evaluated using circuit compatible HSPICE model. The expression for drain current has been derived in terms of surface potential, specific voltage ?i(S/D), subband minima, source / drain Fermi levels and gate voltage. The PDP and EDP of basic carbon nanotube field effect transistor based logic devices have been investigated based on this HSPICE model.

Reference

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Keywords

Carbon NanotubesCNT), HSPICE, Ambipolarity, CNTFET.