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Comparative Study of TURBO, LDPC Encoder and Decoder

Pravin R. Giradkar, Manish Chavhan Published in Network Application

IJAIS Proceedings on 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
Year of Publication: 2013
© 2012 by IJAIS Journal
10.5120/ncipet1301
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  1. Pravin R Giradkar and Manish Chavhan. Article: COMPARATIVE STUDY of TURBO, LDPC ENCODER and DECODER. IJAIS Proceedings on 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) NCIPET(1):1-4, November 2013. BibTeX

    @article{key:article,
    	author = "Pravin R. Giradkar and Manish Chavhan",
    	title = "Article: COMPARATIVE STUDY of TURBO, LDPC ENCODER and DECODER",
    	journal = "IJAIS Proceedings on 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)",
    	year = 2013,
    	volume = "NCIPET",
    	number = 1,
    	pages = "1-4",
    	month = "November",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

To assemble heightening information rate for radio communication, existing way, technology turn pathetic, achieving tolerable usable spectrum budget looking at future trust. This survey paper present comparative study between well known encoder and decoder methods which are used for forward error correction. This paper discuss about LDPC, Turbo encoder decoder based on different architecture like , parallel architecture, throughput, efficiency, system hardware implementation, bit rate, block size, propagation delay, Complexity, BER, memory (FPGA) and logic gates (FPGA) required on FPGA. After studying we found turbo coding is mend than former for radio communication.

Reference

  1. Yang Sun, Marjan Karkooti and Joseph R. Cavallaro, high throughput, parallel, scalable ldpc encoder/decoder architecture for ofdm systems: in the proceeding of IEEE standard, Department of Electrical and Computer Engineering, Rice University, Houston, TX, 77005.
  2. Sandi Habinc,Gian Paolo Calzolari,Enrico Vassallo,Development plan for for Turbo Encoder Core and devices implementing the updated CCSDS telemetry channal coding standard: in procedding of IEEE standard,European space research and technology center ,Elecrtical engineering department postbus 299,NL-2200AG Noordwijk. November 1995.
  3. Lei Yang,Hui Liu and C. -J. Richard Shi, Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Check bit -Check Code Decoder: in proceeding IEEE standard Department of Electrical Engineering University of Washington, Seattle, WA 98195 {yanglei,hliu,shi}@ee. washington. edu.
  4. M. Valenti, "Iterative Detection on Decoding for Wireless Communications," PhD dissertation, Virginia Polytechnic Institute and State University, July 1999.
  5. Rajeshwari. M. Banakar, A Lowpower Design Methodology For Turbo Encoder And Decoder : in proceeding IEEE standard, department of electrical engineering indian institute of technology, delhi india. july 2004.
  6. C. Berrou and A. Glavieux, "Near Optimum Error Correcting Coding and Decoding: Turbo Codes," IEEE Transactions on Communications, vol. 44, no. 10, Oct. 1996, pp. 1261-1271
  7. Mohammad M. Mansour and Naresh R. Shanbhag, High-Throughput LDPC Decoders: ieee transactions on very large scale integration systems, vol. 11, no. 6, december 2003.
  8. Jason Kwok-San Lee and Jeremy Thorpe, Memory-Efficient Decoding of LDPC Codes: available at http://www. systems. caltech. edu/jeremy/re earch/papers/research. html.
  9. Marjan Karkooti, Semi parallel architecture for real time LPDC coding: in proceeding of IEEE standard,department of electrical and computer engineering,May 2004.
  10. Naoya Onizawa, Tomokazu Ikeda and Takahiro Hany, 3. 2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm: Research Institute of Electrical Communication, Tohoku University, Sendai, Japan.

Keywords

Low Dencity Check bit Check, LDPC, Turbo, Convolution, Viterbi, Encoder, Decoder, Bit Error rate, Throughput.