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A Novel High-speed Adder-Subtractor Design based on CNFET

by Shimaa I. Sayed, Salah El-Din H. Gamal
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International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 10 - Number 7
Year of Publication: 2016
Authors: Shimaa I. Sayed, Salah El-Din H. Gamal
10.5120/ijais2016451529

Shimaa I. Sayed, Salah El-Din H. Gamal . A Novel High-speed Adder-Subtractor Design based on CNFET. International Journal of Applied Information Systems. 10, 7 ( March 2016), 29-32. DOI=10.5120/ijais2016451529

@article{ 10.5120/ijais2016451529,
author = { Shimaa I. Sayed, Salah El-Din H. Gamal },
title = { A Novel High-speed Adder-Subtractor Design based on CNFET },
journal = { International Journal of Applied Information Systems },
issue_date = { March 2016 },
volume = { 10 },
number = { 7 },
month = { March },
year = { 2016 },
issn = { 2249-0868 },
pages = { 29-32 },
numpages = {9},
url = { https://www.ijais.org/archives/volume10/number7/878-2016451529/ },
doi = { 10.5120/ijais2016451529 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T19:02:51.666519+05:30
%A Shimaa I. Sayed
%A Salah El-Din H. Gamal
%T A Novel High-speed Adder-Subtractor Design based on CNFET
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 10
%N 7
%P 29-32
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with 48% and 11% respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters.

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Index Terms

Computer Science
Information Sciences

Keywords

Single walled CNT Adder-Subtractor High speed and Digital electronics.

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