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A Novel High-speed Adder-Subtractor Design based on CNFET

Shimaa I. Sayed, Salah El-Din H. Gamal. Published in Circuits and Systems

A Novel High-speed Adder-Subtractor Design based on CNFET
International Journal of Applied Information Systems
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Series: Volume 10 Number 7
Authors: Shimaa I. Sayed, Salah El-Din H. Gamal
10.5120/ijais2016451529
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  1. Shimaa I Sayed and Salah El-Din H Gamal. Article: A Novel High-speed Adder-Subtractor Design based on CNFET. International Journal of Applied Information Systems 10(7):29-32, March 2016. BibTeX

    @article{key:article,
	author = "Shimaa I. Sayed and Salah El-Din H. Gamal",
	title = "Article: A Novel High-speed Adder-Subtractor Design based on CNFET",
	journal = "International Journal of Applied Information Systems",
	year = 2016,
	volume = 10,
	number = 7,
	pages = "29-32",
	month = "March",
	note = "Published by Foundation of Computer Science (FCS), NY, USA"
}

Abstract

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with 48% and 11% respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters.

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Keywords

Single walled CNT, Adder-Subtractor, High speed, and Digital electronics.