CFP last date
15 May 2024
Call for Paper
June Edition
IJAIS solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 15 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Analysis of ANN Training Algorithms for Hand Geometry-Based Access Control

Kazeem B. Adedeji Apena Waliu O. Adu Michael R.
Random Articles
Reseach Article

Design and Development of Vedic Mathematics based BCD Adder

by C. Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat, J Mohan Kumar
journal cover thumbnail

International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 6 - Number 9
Year of Publication: 2014
Authors: C. Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat, J Mohan Kumar
10.5120/ijais14-451119

C. Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat, J Mohan Kumar . Design and Development of Vedic Mathematics based BCD Adder. International Journal of Applied Information Systems. 6, 9 ( March 2014), 16-21. DOI=10.5120/ijais14-451119

@article{ 10.5120/ijais14-451119,
author = { C. Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat, J Mohan Kumar },
title = { Design and Development of Vedic Mathematics based BCD Adder },
journal = { International Journal of Applied Information Systems },
issue_date = { March 2014 },
volume = { 6 },
number = { 9 },
month = { March },
year = { 2014 },
issn = { 2249-0868 },
pages = { 16-21 },
numpages = {9},
url = { https://www.ijais.org/archives/volume6/number9/605-1119/ },
doi = { 10.5120/ijais14-451119 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T18:53:12.815470+05:30
%A C. Sundaresan
%A C V S Chaitanya
%A P R Venkateswaran
%A Somashekara Bhat
%A J Mohan Kumar
%T Design and Development of Vedic Mathematics based BCD Adder
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 6
%N 9
%P 16-21
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In a conventional Binary Coded Decimal (BCD) representation is used in the scientific and computing calculation. Now they are also started to have impact in the processing unit. The only overhead in the converting the value from decimal to binary, processing and converting back to decimal. The direct reproduction of decimal value in computation produces the significant improvement in conversion and processing time. This paper is the extended version of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. When the design is simulated for the corner cases, the design was not responding as expected and we have proposed the modified design.

References
  1. W Buchholz Fingers or Fists? (The Choice of Decimal or Binary Representation). Communications of the ACM, vol. 2, issue 12, pg 3–11, December 1959.
  2. A. H. Burks, H. H. Goldstein, and J. von Neumann. Preliminary Discussion of The Logical Design of An Electronic Computing Instrument. Technical report, Institute for Advanced Study, June 1946.
  3. M. F. Cowlishaw. Decimal Floating-Point: Algorism for Computers. In Proceedings of 16th IEEE Symposium onComputer Arithmetic, pages 104–111, June 2003
  4. M. M. Mano. Digital Design, pages 129–131. Prentice Hall, third edition, 2002.
  5. I. S. Hwang. High Speed Binary and Decimal Arithmetic Unit. United States Patent, (4,866,656), September 1989.
  6. B. Shirazi, D. Y. Y. Young, and C. N. Zhang. RBCD: Redundant Binary Coded Decimal Adder. In IEEE Proceedings, Part E, No. 2, volume 136, pages 156–160, March 1989.
  7. M. S. Schmookler and A. W. Weinberger. High Speed Decimal Addition. IEEE Transactions on Computers, C-20:862– 867, Aug. 1971.
  8. J. D. Thompson, N. Karra, and M. J. SchulteB. A 64-Bit Decimal Floating-Point Adder. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 297– 298, February 2004.
  9. P. M. Kogge and H. S. Stone. A Parallel Algorithm for The Efficient Solution of a General Class of Recurrence Equations. IEEE Trans. on Computers, C-22(8), Aug. 1973.
  10. Alp Arslan Bayrakci and Ahmet Akkas. Reduced Delay BCD Adder. IEEE, 2007.
Index Terms

Computer Science
Information Sciences

Keywords

BCD adder decimal adder higher valence adder adder.

Powered by PhDFocusTM