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Design and Development of Vedic Mathematics based BCD Adder

C. Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat, J Mohan Kumar Published in Communications

International Journal of Applied Information Systems
Year of Publication: 2014
© 2013 by IJAIS Journal
10.5120/ijais14-451119
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  1. C Sundaresan, C V S Chaitanya, P R Venkateswaran, Somashekara Bhat and Mohan J Kumar. Article: Design and Development of Vedic Mathematics based BCD Adder. International Journal of Applied Information Systems 6(9):16-21, March 2014. BibTeX

    @article{key:article,
    	author = "C. Sundaresan and C V S Chaitanya and P R Venkateswaran and Somashekara Bhat and J Mohan Kumar",
    	title = "Article: Design and Development of Vedic Mathematics based BCD Adder",
    	journal = "International Journal of Applied Information Systems",
    	year = 2014,
    	volume = 6,
    	number = 9,
    	pages = "16-21",
    	month = "March",
    	note = "Published by Foundation of Computer Science, New York, USA"
    }
    

Abstract

In a conventional Binary Coded Decimal (BCD) representation is used in the scientific and computing calculation. Now they are also started to have impact in the processing unit. The only overhead in the converting the value from decimal to binary, processing and converting back to decimal. The direct reproduction of decimal value in computation produces the significant improvement in conversion and processing time. This paper is the extended version of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. When the design is simulated for the corner cases, the design was not responding as expected and we have proposed the modified design.

Reference

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  10. Alp Arslan Bayrakci and Ahmet Akkas. Reduced Delay BCD Adder. IEEE, 2007.

Keywords

BCD adder, decimal adder, higher valence adder, adder.