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Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis

Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva in Information Sciences

International Journal of Applied Information Systems
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors:Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva
10.5120/ijais2018451758
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  1. Tiago Silva Almeida, Pedro Henrique Castro Lima, Rafael Lima Carvalho and Warley Gramacho Silva. Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis. International Journal of Applied Information Systems 12(13):1-7, May 2018. URL, DOI BibTeX

    @article{10.5120/ijais2018451758,
    	author = "Tiago da Silva Almeida and Pedro Henrique de Castro Lima and Rafael Lima de Carvalho and Warley Gramacho da Silva",
    	title = "Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis",
    	journal = "International Journal of Applied Information Systems",
    	issue_date = "May 2018",
    	volume = 12,
    	number = 13,
    	month = "May",
    	year = 2018,
    	issn = "2249-0868",
    	pages = "1-7",
    	url = "http://www.ijais.org/archives/volume12/number13/1029-2018451758",
    	doi = "10.5120/ijais2018451758",
    	publisher = "Foundation of Computer Science (FCS), NY, USA",
    	address = "New York, USA"
    }
    

Abstract

The development of digital systems requires an extreme attention by the circuit designer due to the different abstraction domains that the same system could be. This fact brings many issues and challenges in circuit design, due to the wide range of levels and representations. There are many details the designer have to concern, such as area, performance, architecture and energy consumption. To aid in different representations, this paper brings up a framework that is able to translate schematics of digital systems built using the CAD tool Logisim, into implementations at the hardware description level, to help in issues and to teach future designers in the academy. It was built a checker of a model after and before of the synthesis to ensure the model validity and tests. The HDL chosen was SystemC because it is easy to compile and check in any open source C++ compiler. The set of tests applied to 41 different circuits models have shown that the proposed tool works effectively ensuring the desired output.

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Keywords

Digital Systems, Synthesis, Computer Aided Design, Logisim