|International Journal of Applied Information Systems
|Foundation of Computer Science (FCS), NY, USA
|Volume 12 - Number 13
|Year of Publication: 2018
|Authors: Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva
Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva . Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis. International Journal of Applied Information Systems. 12, 13 ( May 2018), 1-7. DOI=10.5120/ijais2018451758
The development of digital systems requires an extreme attention by the circuit designer due to the different abstraction domains that the same system could be. This fact brings many issues and challenges in circuit design, due to the wide range of levels and representations. There are many details the designer have to concern, such as area, performance, architecture and energy consumption. To aid in different representations, this paper brings up a framework that is able to translate schematics of digital systems built using the CAD tool Logisim, into implementations at the hardware description level, to help in issues and to teach future designers in the academy. It was built a checker of a model after and before of the synthesis to ensure the model validity and tests. The HDL chosen was SystemC because it is easy to compile and check in any open source C++ compiler. The set of tests applied to 41 different circuits models have shown that the proposed tool works effectively ensuring the desired output.