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Reseach Article

Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis

by Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva
International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 12 - Number 13
Year of Publication: 2018
Authors: Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva
10.5120/ijais2018451758

Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva . Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis. International Journal of Applied Information Systems. 12, 13 ( May 2018), 1-7. DOI=10.5120/ijais2018451758

@article{ 10.5120/ijais2018451758,
author = { Tiago da Silva Almeida, Pedro Henrique de Castro Lima, Rafael Lima de Carvalho, Warley Gramacho da Silva },
title = { Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis },
journal = { International Journal of Applied Information Systems },
issue_date = { May 2018 },
volume = { 12 },
number = { 13 },
month = { May },
year = { 2018 },
issn = { 2249-0868 },
pages = { 1-7 },
numpages = {9},
url = { https://www.ijais.org/archives/volume12/number13/1029-2018451758/ },
doi = { 10.5120/ijais2018451758 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T19:09:06.220813+05:30
%A Tiago da Silva Almeida
%A Pedro Henrique de Castro Lima
%A Rafael Lima de Carvalho
%A Warley Gramacho da Silva
%T Improvement in Logisim to Digital Systems Simulation in Higher Levels of Abstraction and Synthesis
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 12
%N 13
%P 1-7
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The development of digital systems requires an extreme attention by the circuit designer due to the different abstraction domains that the same system could be. This fact brings many issues and challenges in circuit design, due to the wide range of levels and representations. There are many details the designer have to concern, such as area, performance, architecture and energy consumption. To aid in different representations, this paper brings up a framework that is able to translate schematics of digital systems built using the CAD tool Logisim, into implementations at the hardware description level, to help in issues and to teach future designers in the academy. It was built a checker of a model after and before of the synthesis to ensure the model validity and tests. The HDL chosen was SystemC because it is easy to compile and check in any open source C++ compiler. The set of tests applied to 41 different circuits models have shown that the proposed tool works effectively ensuring the desired output.

References
  1. Google-gson, 2012.
  2. Logisim evolution git repository, 2014.
  3. Logisim: a graphical tool for designing and simulation logic circuit, March 2017.
  4. S. S. Abrar, M. Jenihhin, J. Raik, S. Kiran A., and C. Babu. Performance analysis of cosimulating processor core in vhdl and systemc. In 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI), pages 563–568, Aug 2013.
  5. Ravi Sethi Jeffrey D. Ullman Alfred V. Aho, Monica S. Lam. Compilers: principles, techniques, & tools. Pearson/ Addison Wesley, 2nd ed edition, 2007.
  6. I. E. Bennour. Systemc tlm2-protocol consistency checker using petri net. In 2016 11th International Design Test Symposium (IDT), pages 193–198, Dec 2016.
  7. Carl Burch. Logisim: a graphical tool for designing and simulation logic circuit, March 2014.
  8. D. C. Caf, F. V. dos Santos, C. Hardebolle, C. Jacquet, and F. Boulanger. Multi-paradigm semantics for simulating sysml models using systemc-ams. In Proceedings of the 2013 Forum on specification and Design Languages (FDL), pages 1–8, Sept 2013.
  9. C. Cote and Z. Zilic. Automated systemc to vhdl translation in hardware/software codesign. In 9th International Conference on Electronics, Circuits and Systems, volume 2, pages 717–720 vol.2, 2002.
  10. D. D. Gajski. System-level synthesis: From specification to transaction level models. In 2009 International Conference on Communications, Circuits and Systems, pages 1134– 1138, July 2009.
  11. A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski, and J. Teich. Electronic system-level synthesis methodologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10):1517– 1530, Oct 2009.
  12. M. Goli, J. Stoppe, and R. Drechsler. Automatic equivalence checking for systemc-tlm 2.0 models against their formal specifications. In Design, Automation Test in Europe Conference Exhibition (DATE), 2017, pages 630–633, March 2017.
  13. S. Gupta, N. Dutt, R. Gupta, and A. Nicolau. Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits. IEE Proceedings - Computers and Digital Techniques, 150(5):330–7–, Sept 2003.
  14. S. Ouadjaout and D. Houzet. Rapid integration of reusable functional ips with systemc vci adapters. In Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004., pages 236–239, Dec 2004.
  15. Terence Parr. The Definitive ANTLR 4 Reference. Pragmatic Bookshelf, 2nd edition, 2013.
  16. Ken Thompson. Programming techniques: Regular expression search algorithm. Commun. ACM, 11(6):419–422, June 1968.
  17. Chen Xi, Lu Jian Hua, Zhou ZuCheng, and Shang YaoHui. Modeling systemc design in uml and automatic code generation. In Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., volume 2, pages 932–935 Vol. 2, Jan 2005.
Index Terms

Computer Science
Information Sciences

Keywords

Digital Systems Synthesis Computer Aided Design Logisim